For many years data flow Petri nets have proved their efficiency in modelling parallel processings. Moreover, an automatic method for their design would be greatly useful. The aim of this paper is to present a methodology for hardware / software codesign based on the principle of factorization / defactorization and thus, to obtain an optimized implementation with the best possible compromise between hardware resources amount and latency, while respecting defined constraints. The search of adequate intermediate factorization / defactorization modelling is very important. In fact, an algorithm can be decomposed into a non-parallelizable part and a parallelizable part. On this latest part, a factoriztion may lead to reduce the amount of hardware resources, while a defactorization has influence on latency. The achievement of a unique optimal solution is not insured, but satisfying optimized solutions can be obtained. First results for several factorizations / defactorizations of a Matrix Vector Product Petri Net description are presented and discussed.