Several studies on hardware/software codesign proved the necessity of an appropriate modeling in order to achieve a correct implementation on chips, as regards hardware resources and execution times. Taking into account the processing speed of programmable components, a data flow Petri nets based model using the factorization of repetitive operations has been developed. Factorization frontiers and specific operators are defined, as well as control units. Processing is therefore not fully parallel but also sequential. The unification of factorized data flow and control flow Petri nets constitutes architectural Petri nets. This new approach allows a gain in hardware resources whereas time lengthening can be acceptable for real-time applications